Conventional microprocessors typically include a Universal Asynchronous Receiver/Transmitter (UART) interface for communicating with other entities. A UART interface requires a transmit pin (TX), a receive pin (RX), a Request to Send (RTS) pin, and a Clear to Send (CTS) pin. The UART interface uses an oversampling clock that is 16 times the bit rate. So each received bit is represented by sixteen samples. The UART transmission is very straightforward: to send a binary one, a transmitting UART interface drives its TX pin to the power supply voltage VDD for the duration of the bit period as determined by sixteen cycles of its oversampling clock. The receiving UART interface counts its bit period using its own oversampling clock. Transmission of a binary zero is just the complement: the transmitting UART interface grounds its transmit pin for the duration of the bit period as determined by its oversampling clock cycling the appropriate number of times. The UART interface uses a Request to Send (RTS) pin and a Clear to Send (CTS) pin for flow control. In particular, a receiving UART interface indicates that it is ready to receive data by asserting its RTS pin to a power supply voltage VDD that is received at the transmitting UART interface on its CTS pin. So a transmitting UART interface only transmits when it sees the voltage on it CTS pin being asserted. The resulting data transmission is in frames of eight bits.
Although UART interfaces are simple and relatively robust, its over-sampling clock consumes substantial power as it must oscillate regardless of whether the UART interface is transmitting or receiving data. In addition, UART's frame size is fixed at eight bits. If the frame size is increased, the timing requirements on the oversampling clock (with regard to keeping the transmitter's clock sufficiently aligned with the receiver's clock) become more and more stringent. Accordingly, there is a need in the art for a low-power synchronous data interface that accommodates flexible frame lengths without the use of an oversampling clock.